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| IS61LV2568 256K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES * High-speed access times: 8, 10, 12 and 15 ns * High-performance, low-power CMOS process * Multiple center power and ground pins for greater noise immunity * Easy memory expansion with CE and OE options * CE power-down * Low power: 540 mW @ 10 ns 36 mW standby mode * TTL compatible inputs and outputs * Single 3.3V 10% power supply * Packages available: - 36-pin 400-mil SOJ - 44-pin TSOP (Type II) ISSI (R) DECEMBER 2000 DESCRIPTION The ISSI IS61LV2568 is a very high-speed, low power, 262,144-word by 8-bit CMOS static RAM. The IS61LV2568 is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 36mW (max.) with CMOS input levels. The IS61LV2568 operates from a single 3.3V power supply and all inputs are TTL-compatible. The IS61LV2568 is available in 36-pin 400-mil SOJ, and 44-pin TSOP (Type II) packages. FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K X 8 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE WE CONTROL CIRCUIT ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 12/19/00 1 IS61LV2568 PIN CONFIGURATION 36-Pin SOJ A4 A3 A2 A1 A0 CE I/O0 I/O1 Vcc GND I/O2 I/O3 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A5 A6 A7 A8 OE I/O7 I/O6 GND Vcc I/O5 I/O4 A9 A10 A11 A12 NC NC ISSI 44-Pin TSOP (Type II) NC NC A4 A3 A2 A1 A0 CE I/O0 I/O1 Vcc GND I/O2 I/O3 WE A17 A16 A15 A14 A13 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A5 A6 A7 A8 OE I/O7 I/O6 GND Vcc I/O5 I/O4 A9 A10 A11 A12 NC NC NC NC (R) PIN DESCRIPTIONS A0-A17 CE OE WE I/O0-I/O7 Vcc GND NC Address Inputs Chip Enable Input Output Enable Input Write Enable Input Bidirectional Ports Power Ground No Connection TRUTH TABLE Mode WE CE H L L L OE X H L X I/O Operation Vcc Current High-Z High-Z DOUT DIN ISB1, ISB2 ICC ICC ICC Not Selected X (Power-down) Output Disabled H Read H Write L ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VTERM TBIAS TSTG PD Parameter Supply voltage with Respect to GND Terminal Voltage with Respect to GND Temperature Under Bias Com. Ind. Storage Temperature Power Dissipation Value -0.5 to +4.6 -0.5 to Vcc + 0.5 -10 to +85 -45 to +90 -65 to +150 1.0 Unit V V C C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 12/19/00 IS61LV2568 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 10% 3.3V 10% ISSI (R) DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage(1) Input LOW Voltage(1) Input Leakage Output Leakage GND - VIN - VCC GND - VOUT - VCC, Outputs Disabled Com. Ind. Com. Ind. Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 -- 2.0 -0.3 -1 -5 -1 -5 Max. -- 0.4 VCC + 0.3 0.8 1 5 1 5 Unit V V V V A A Note: 1. VIL(min) = -0.3V (DC); VIL(min) = -2.0V (pulse width - 2.0 ns). VIH(max) = VCC + 0.3V (DC); VIH(max) = Vcc + 2.0V (pulse width - 2.0 ns). POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC ISB1 Parameter Vcc Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = Max. VCC = Max., VIN = VIH or VIL CE * VIH, f = max VCC = Max., CE - VCC - 0.2V, VIN > VCC - 0.2V, or VIN - 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. -8 ns Min. Max. -- -- -- -- -- -- 150 160 50 60 10 20 -10 ns Min. Max. -- -- -- -- -- -- 125 135 40 50 10 20 -12 ns Min. Max. -- -- -- -- -- -- 110 120 35 45 10 20 -15 ns Min. Max. -- -- -- -- -- -- 90 100 30 40 10 20 Unit mA mA ISB2 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 12/19/00 3 IS61LV2568 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time - 8 ns Min. Max 8 -- 3 -- -- 0 0 3 0 -- 8 -- 8 3 -- 3 -- 3 -10 ns Min. Max. 10 -- 3 -- -- 0 0 3 0 -- 10 -- 10 4 -- 4 -- 4 -12 ns Min. Max. 12 -- 3 -- -- 0 0 3 0 -- 12 -- 12 5 -- 5 -- 5 -15 ns Min. Max. 15 -- 3 -- -- 0 0 3 0 -- 15 -- 15 6 -- 6 -- 6 ISSI Unit ns ns ns ns ns ns ns ns ns (R) tRC tAA tOHA tACE tDOE tLZOE(2) OE to Low-Z Output tHZOE(2) OE to High-Z Output tLZCE (2) (2) CE to Low-Z Output CE to High-Z Output tHZCE Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 319 3.3V 3.3V 319 OUTPUT 30 pF Including jig and scope 353 OUTPUT 5 pF Including jig and scope 353 Figure 1 Figure 2 4 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 12/19/00 IS61LV2568 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL) t RC ADDRESS ISSI (R) t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ1.eps READ CYCLE NO. 2(1,3) (CE and OE Controlled) t RC ADDRESS t AA OE t OHA t DOE CE t HZOE t LZOE t ACE t LZCE t HZCE DATA VALID CE_RD2.eps DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 12/19/00 5 IS61LV2568 WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width (OE = HIGH) WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End (3) ISSI - 8 ns Min. Max 8 6.5 6.5 0 0 5 6.5 4 0 -- 0 -- -- -- -- -- -- -- -- -- 3 -- -10 ns Min. Max. 10 8 8 0 0 7 8 5 0 -- 0 -- -- -- -- -- -- -- -- -- 4 -- -12 ns Min. Max. 12 9 9 0 0 8 10 6 0 -- 0 -- -- -- -- -- -- -- -- -- 5 -- -15 ns Min. Max. 15 10 10 0 0 10 11 7 0 -- 0 -- -- -- -- -- -- -- -- -- 6 -- Unit ns ns ns ns ns ns ns ns ns ns ns (R) tWC tSCE tAW tHA tSA tPWE1 tPWE2 tSD tHD tLZWE tHZWE(3) WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC ADDRESS VALID ADDRESS t SA CE t SCE t HA WE t AW t PWE1 t PWE2 t HZWE t LZWE HIGH-Z DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID CE_WR1.eps Note: 1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write. 6 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 12/19/00 IS61LV2568 AC WAVEFORMS WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle) t WC ADDRESS VALID ADDRESS ISSI (R) t HA OE CE LOW t AW t PWE1 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID CE_WR2.eps Note: 1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write. WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE CE LOW t HA LOW t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID CE_WR3.eps Note: 1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 12/19/00 7 IS61LV2568 ISSI (R) ORDERING INFORMATION Commercial Range: 0C to +70C Speed (ns) 8 10 12 15 Order Part No. IS61LV2568-8K IS61LV2568-8T IS61LV2568-10K IS61LV2568-10T IS61LV2568-12K IS61LV2568-12T IS61LV2568-15K IS61LV2568-15T Package 400-mil Plastic SOJ TSOP (Type II) 400-mil Plastic SOJ TSOP (Type II) 400-mil Plastic SOJ TSOP (Type II) 400-mil Plastic SOJ TSOP (Type II) ORDERING INFORMATION Industrial Range: -40C to +85C Speed (ns) 8 10 12 15 Order Part No. IS61LV2568-8KI IS61LV2568-8TI IS61LV2568-10KI IS61LV2568-10TI IS61LV2568-12KI IS61LV2568-12TI IS61LV2568-15KI IS61LV2568-15TI Package 400-mil Plastic SOJ TSOP (Type II) 400-mil Plastic SOJ TSOP (Type II) 400-mil Plastic SOJ TSOP (Type II) 400-mil Plastic SOJ TSOP (Type II) ISSI (R) Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com 8 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 12/19/00 |
Price & Availability of IS61LV2568-12K
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